1. Field of the Invention
The invention relates generally to electronic circuits and more particularly to CMOS logic circuits in which an output is coupled to a feedback path to speed logic state transitions.
2. Description of the Related Art
Referring to the illustrative drawings of FIG. 1 there is shown an earlier TTL to CMOS input buffer logic circuit 10. The circuit includes an input terminal 12 and an internal output node 14. A CMOS inverter circuit 16 which includes a PMOS transistor 18 and an NMOS transistor 22 receives respective input signals at TTL logic levels at the input terminal 12 and provides logically inverted versions of the respectively received signals at CMOS logic levels at the output node 14.
The threshold voltage of the CMOS inverter circuit 16 is adjusted so that the circuit will respond to input signals applied to the input node 12 at TTL logic levels. In the case of the inverter circuit 16 shown in FIG. 1, such threshold voltage shifting is accomplished, at least in part, by the use of PMOS transistor 20 which serves as a current source. Alternatively, threshold voltage shifting could be accomplished by adjusting the gate width of PMOS transistor 18, for example.
One problem commonly experienced by prior CMOS logic circuits such as CMOS inverter circuits of the type in which the threshold voltage is shifted to accommodate TTL logic levels has been a timing skew between the length of time required for a low to high input signal transition to propagate a change in the output voltage at node 14 and the length of time required for a high to low input signal transition to propagate a change in the output voltage. In particular, the high to low transitions often are propagated more slowly, at least in part, due to the relatively weak PMOS pull-up used to achieve the desired TTL threshold voltage level.
An earlier solution to this problem of timing skew has been to actively pull-up the voltage at the output node 14. PMOS transistor 24, for example, serves as a pull-up for the internal output node 14 in the course of respective high to low transitions of the input signal provided to terminal 12. By pulling up the output node voltage, the PMOS transistor 24 speeds the transition of the output signal from low to high voltage levels in response to transitions of the input signal from high to low voltage levels. It will be understood, of course, that the output signal at node 14 is an inverted version of the input signal provided at input terminal 12.
Therefore, in earlier CMOS logic circuits such as TTL to CMOS input buffers, an active pull-up device has been used to reduce the timing skew between high to low and low to high transitions. During high to low input signal transitions of the exemplary earlier buffer circuit 10 of FIG. 1, for example, feedback inverter 26 rapidly senses the transitioning of the output signal at node 14 from low to high voltage levels, and in response, provides via feedback path 28 a low logic level signal to the gate of PMOS transistor 24 which causes that transistor to turn on. The turning on of transistor 24, in turn, tends to pull-up the voltage level of the output node 14.
While earlier TTL to CMOS buffer circuits of the type described above generally have been acceptable, there have been shortcomings with their use. More specifically, in the course of input signal transitions from low to high voltage levels, the NMOS transistor 22 is turned on, and the output signal at the output node 14 undergoes a transition from a high to a low voltage level. Unfortunately, during such transitions there is a time interval during which both the NMOS transistor 22 and the PMOS pull-up transistor 24 simultaneously are turned on. During such intervals, the NMOS transistor 22 operates in opposition to the PMOS transistor 24. Such simultaneous activation of these two transistors can lead to an increase in the threshold voltage required to overcome the effects of the pull-up by transistor 24. Furthermore, such simultaneous activation can lead to an increase in the time required for an input signal transition from a low to a high level to propagate a change in the logic level of the output signal.
Thus, there has been a need for a logic circuit in which the timing skew between high to low and low to high input signal transitions can be reduced while maintaining the desired TTL input threshold for the input signal and without resulting in an increase in the time required to propagate low to high input signal transitions. The present invention meets these needs.